As technology scales, transistor performance is not improving accordingly. In order to increase transistor performance, various processes have been implemented to apply stress to the transistor channel region to enhance carrier mobility. Compressive stress enhances hole mobility when applied parallel to the current flow in a p-type metal-oxide-semiconductor (PMOS) transistor. One method to apply compressive stress in PMOS transistors is to remove silicon from the source and drain regions and replace it with epitaxially grown silicon germanium (SiGe). Another method is to deposit a compressive contact etch stop layer over the PMOS transistors.
For n-type metal-oxide-semiconductor (NMOS) transistors, applying tensile stress either perpendicular or parallel to the current flow enhances electron mobility. One method of applying tensile stress to the channel region in an NMOS transistor is to deposit a tensile contact etch stop layer over the NMOS transistor.
Dual stress liner (DSL) technology has been developed to deposit a compressive contact etch stop layer over the PMOS to enhance hole mobility and to deposit a tensile contact etch stop layer over the NMOS to enhance electron mobility. The DSL technology involves multiple depositions and patterning and etching steps to remove the tensile liner from PMOS areas and also to remove compressive liner from the NMOS areas. These additional steps add cost to the process flow.
To reduce cost on cost sensitive integrated circuits, single stress liner (SSL) technology may be employed. For example, a tensile etch stop liner may be deposited over both the NMOS and PMOS transistors. While this boosts the performance of the NMOS transistors, it degrades the performance of the PMOS transistors.
One method to reduce the detrimental effects of SSL is to add a pattern and implant stress reducing atoms. The implanted atoms cause implant damage in the stress film which reduces stress.
As is illustrated in FIG. 1, the usual practice is to use the nwell mask 110 to pattern the stress reduction implant. Typically the boundary 112 of the nwell implant mask 110 lies about midway between the NMOS (active 104 and gate 102) and PMOS (active 108 and gate 106) transistors. The nwell mask 110 is open over the PMOS transistor so the stress reduction implant reduces the stress of a tensile SSL layer over the PMOS transistor and reduces the detrimental effect tensile stress has on the PMOS transistor.